1. Field of the Invention
This invention relates to silicide fabrication, and more particularly to a method for fabricating a self-aligned silicide (salicide) layer by chemical vapor deposition.
2. Description of Related Art
At a deep sub-micron level of semiconductor fabrication technologies, line width, contact area, and junction depth are greatly reduced. In order to effectively enhance device performance, reduce device resistance, and reduce device resistance-capacitance (RC) delay, silicide has gradually taken the place of polysilicon to form conductive parts, such as a gate, or interconnects. A silicide layer is usually formed by triggering a reaction between a metallic material and silicon of a substrate through a rapid thermal annealing process. After reaction, a silicide material is thereby formed on a silicon interface of the substrate. The reaction process usually includes an environmental gas, such as nitrogen or argon. The silicide material usually includes titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, molybdenum silicide, or platinum silicide, of which titanium silicide is most widely used because its conductivity is relatively higher and it can be easily controlled in fabrication.
Conventionally, a layer of titanium metal is formed over the silicon substrate by sputtering deposition. A rapid thermal process (RTP) is performed to trigger a reaction between the titanium metal layer and the silicon atoms of the silicon substrate so as to form a titanium salicide layer.
However, as the device dimension is greatly reduced, the quality of the titanium salicide layer may be degraded due to an overly reduced dimension. The overly reduced dimension often causes too much contact stress or too few of nucleation sites, resulting in a variation of the content ratio of titanium salicide, and further resulting in a poor quality of the titanium salicide layer. A sheet resistance is then raised. The operation performance is unavoidably degraded.